// ******************************************************************************
// Copyright     :  Copyright (C) 2020, Hisilicon Technologies Co. Ltd.
// File name     :  pcie4_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2020/07/29 22:14:57 Create file
// ******************************************************************************

#ifndef PCIE4_REG_OFFSET_H
#define PCIE4_REG_OFFSET_H

/* HIPCIEC_AP_IOB_RX_COM_REG Base address of Module's Register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE (0x4000)

/* **************************************************************************** */
/*                      HIPCIEC_AP_IOB_RX_COM_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x20) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x40) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x60) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x80) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0xA0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0xC0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0xE0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x100) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x120) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x140) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x160) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x180) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x1A0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x1C0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x1E0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_16_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x200) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_17_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x220) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_18_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x240) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_19_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x260) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_20_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x280) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_21_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x2A0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_22_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x2C0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_23_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x2E0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_24_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x300) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_25_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x320) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_26_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x340) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_27_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x360) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_28_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x380) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_29_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x3A0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_30_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x3C0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_31_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x3E0) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_32_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x400) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_33_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x420) /* IOB RX address transition unit control register0.Common information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x24) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x44) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x64) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x84) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0xA4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0xC4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0xE4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x104) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x124) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x144) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x164) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x184) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x1A4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x1C4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x1E4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_16_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x204) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_17_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x224) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_18_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x244) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_19_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x264) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_20_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x284) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_21_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x2A4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_22_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x2C4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_23_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x2E4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_24_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x304) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_25_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x324) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_26_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x344) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_27_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x364) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_28_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x384) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_29_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x3A4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_30_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x3C4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_31_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x3E4) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_32_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x404) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_33_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x424) /* IOB RX address transition unit control information register1.TLP information. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x28) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x48) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x68) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x88) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0xA8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0xC8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0xE8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x108) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                       \
        0x128) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x148) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x168) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x188) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x1A8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x1C8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x1E8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_16_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x208) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_17_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x228) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_18_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x248) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_19_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x268) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_20_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x288) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_21_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x2A8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_22_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x2C8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_23_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x2E8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_24_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x308) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_25_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x328) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_26_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x348) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_27_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x368) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_28_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x388) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_29_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x3A8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_30_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x3C8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_31_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x3E8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_32_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x408) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_33_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x428) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x4C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x6C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x8C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xCC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xEC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x14C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x16C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1CC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1EC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_16_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_17_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x22C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_18_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x24C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_19_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x26C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_20_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x28C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_21_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2AC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_22_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2CC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_23_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2EC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_24_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x30C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_25_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x32C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_26_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x34C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_27_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x36C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_28_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x38C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_29_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3AC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_30_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3CC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_31_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3EC) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_32_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x40C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_33_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x42C) /* IOB RX address transition unit region size low 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x10) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x30) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x50) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x70) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x90) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0xB0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0xD0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0xF0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x110) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x130) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x150) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x170) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x190) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x1B0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x1D0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x1F0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_16_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x210) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_17_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x230) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_18_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x250) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_19_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x270) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_20_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x290) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_21_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x2B0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_22_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x2D0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_23_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x2F0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_24_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x310) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_25_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x330) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_26_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x350) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_27_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x370) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_28_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x390) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_29_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x3B0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_30_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x3D0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_31_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x3F0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_32_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x410) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_33_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                          \
        0x430) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x14) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x34) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x54) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x74) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x94) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x114) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x134) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x154) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x174) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x194) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_16_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x214) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_17_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x234) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_18_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x254) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_19_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x274) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_20_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x294) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_21_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2B4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_22_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2D4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_23_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2F4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_24_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x314) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_25_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x334) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_26_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x354) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_27_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x374) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_28_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x394) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_29_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3B4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_30_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3D4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_31_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3F4) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_32_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x414) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_33_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x434) /* IOB RX address transition unit base address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x18) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x38) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x58) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x78) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x98) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0xB8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0xD8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0xF8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x118) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x138) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x158) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x178) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x198) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x1B8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x1D8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x1F8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_16_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x218) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_17_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x238) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_18_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x258) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_19_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x278) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_20_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x298) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_21_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x2B8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_22_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x2D8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_23_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x2F8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_24_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x318) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_25_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x338) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_26_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x358) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_27_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x378) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_28_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x398) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_29_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x3B8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_30_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x3D8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_31_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x3F8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_32_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x418) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_33_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                         \
        0x438) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x5C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x7C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x9C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xDC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xFC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x13C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x17C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x19C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1DC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1FC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_16_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x21C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_17_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_18_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x25C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_19_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x27C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_20_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x29C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_21_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2BC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_22_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2DC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_23_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2FC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_24_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x31C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_25_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x33C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_26_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x35C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_27_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x37C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_28_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x39C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_29_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3BC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_30_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3DC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_31_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3FC) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_32_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x41C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_33_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x43C) /* IOB RX address transition unit target address high 32bit. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CNT_CLR_CE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA00) /* counter type control register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA40) /* Counter of RX received NP */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA80) /* Counter of RX received NP */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC0) /* Counter of RX received NP */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA44) /* Counter of RX Received P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA84) /* Counter of RX Received P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC4) /* Counter of RX Received P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA48) /* Counter of RX Received CPL */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA88) /* Counter of RX Received CPL */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC8) /* Counter of RX Received CPL */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_MSIX_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA4C) /* Counter of RX MSI/MSI-X interrupt */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_MSIX_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA8C) /* Counter of RX MSI/MSI-X interrupt */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_MSIX_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xACC) /* Counter of RX MSI/MSI-X interrupt */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_P2P_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA50) /* Counter of RX Received NP for P2P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_P2P_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA90) /* Counter of RX Received NP for P2P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_P2P_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAD0) /* Counter of RX Received NP for P2P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_P2P_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA54) /* Counter of RX Received P for P2P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_P2P_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA94) /* Counter of RX Received P for P2P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_P2P_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAD4) /* Counter of RX Received P for P2P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_P2P_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA58) /* Counter of RX Received CPL for P2P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_P2P_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA98) /* Counter of RX Received CPL for P2P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_P2P_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAD8) /* Counter of RX Received CPL for P2P */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_ODR_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA60) /* Counter of RX Received NP to ODR channel */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_ODR_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAA0) /* Counter of RX Received NP to ODR channel */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_ODR_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAE0) /* Counter of RX Received NP to ODR channel */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_ODR_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA64) /* Counter of RX Received P to ODR channel */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_ODR_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAA4) /* Counter of RX Received P to ODR channel */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_ODR_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAE4) /* Counter of RX Received P to ODR channel */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_HAQ_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA68) /* Counter of HAQ operation */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_HAQ_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAA8) /* Counter of HAQ operation */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_HAQ_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAE8) /* Counter of HAQ operation */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_AER_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA70) /* Counter of RX Error to AER */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_AER_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAB0) /* Counter of RX Error to AER */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_AER_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAF0) /* Counter of RX Error to AER */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_AER_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA74) /* Counter of RX Error to AER */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_AER_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAB4) /* Counter of RX Error to AER */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_AER_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAF4) /* Counter of RX Error to AER */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PRE_ERR_STS_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB80) /* Error status of IOB_RX preprocess */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PRE_ERR_STS_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB84) /* Error status of IOB_RX preprocess */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PRE_ERR_STS_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB88) /* Error status of IOB_RX preprocess */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_PKT_NUM_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB90) /* Current pkt_num of RX_NP Request */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_PKT_NUM_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBA0) /* Current pkt_num of RX_NP Request */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_PKT_NUM_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBB0) /* Current pkt_num of RX_NP Request */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_PKT_NUM_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB94) /* Current pkt_num of RX_P Request */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_PKT_NUM_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBA4) /* Current pkt_num of RX_P Request */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_PKT_NUM_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBB4) /* Current pkt_num of RX_P Request */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_PKT_NUM_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB98) /* Current pkt_num of RX_CPL Request */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_PKT_NUM_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBA8) /* Current pkt_num of RX_CPL Request */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_PKT_NUM_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBB8) /* Current pkt_num of RX_CPL Request */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_ATS_INV_LKDN_CLR_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10B0) /* APAT ATS invalidate clear status when linkdown occurs */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_SYNC_WAIT_RLS_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                        \
        0x10B4) /* APAT entry number waiting to be release when the cmd_sync request received */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IDLE_SET_CFG_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10BC) /* APAT IDLE status force set configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RD_IDX_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10C0) /* APAT request entry index for read */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RD_DONE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10C4) /* APAT request entry read finish */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RDATA0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10C8) /* APAT request entry read data [31:0] */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RDATA1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10CC) /* APAT request entry read data [63:32] */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RDATA2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10D0) /* APAT request entry read data [95:64] */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RDATA3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10D4) /* APAT request entry read data [127:96] */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_TRANSLATION_IDLE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10D8) /* APAT ATS translation idle indication */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_PRI_IDLE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10DC) /* APAT ATS PRI service idle indication */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_RO_CE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10E0) /* APAT interrupt read only status for correctable error */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_RO_NFE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10E4) /* APAT interrupt read only status for non-fatal error */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_RO_FE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10E8) /* APAT interrupt read only status for fatal error */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_SEVERITY_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10EC) /* APAT interrupt severity configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_SET_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10F0) /* APAT interrupt set configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_MASK_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10F4) /* APAT interrupt mask configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_STATUS_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10F8) /* APAT interrupt status */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_RO_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10FC) /* APAT interrupt read only status */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TRANSLATION_CFG_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1100) /* Control some behaviours of the inbound request translatioin */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TRANSLATION_RETRY_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1104) /* Control the TLB lookup request retry behaviour */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_SYNC_TIMEOUT_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1108) /* SYNC response time out threshold */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_LKUP_STATS_CFG_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1110) /* Config parameters that are used by performance profiling */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_LKUP_REQ_PCT_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1114) /* APAT lookup request DFX */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_LKUP_REQ_LENGTH_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1118) /* APAT lookup request statistics */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_NP_LKUP_REQ_LENGTH_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x111C) /* APAT NP lookup request length */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_NP_LKUP_LATENCY_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1120) /* APAT NP lookup latency */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_P_LKUP_LATENCY_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1124) /* APAT P lookup latency */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_HINT_CFG_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1140) /* Hint generated config */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_FIFO_DFX_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1144) /* TLB predictor FIFO DFx */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_PAGE_SIZE_CACHE_PERFORMANCE_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1148) /* 16KB/64KB/2MB page size cache hit and miss ratio */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_PAGE_SIZE_CACHE_PERFORMANCE_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x114C) /* 16KB/64KB/2MB page size cache evict and not_replace ratio */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_LOCK_CACHE_PERFORMANCE_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1150) /* LOCK hint cache hit and miss ratio */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_LOCK_CACHE_PERFORMANCE_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1154) /* LOCK hint cache evict and not_replace ratio */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_RAM_PARITY_DFX_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1158) /* RAM parity check DFX */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNXT_RAM_ECC_CFG_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x115C) /* RAM ECC inject control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNXT_RAM_ECC_STS_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1160) /* RAM ECC status */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_FST_RSP_FAULT_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1164) /* first response fault from SMMU recorder #0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_FST_RSP_FAULT_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1168) /* first response fault from SMMU recorder #1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_FST_RSP_FAULT_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x116C) /* first response fault from SMMU recorder #2 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_FST_RSP_FAULT_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1170) /* first response fault from SMMU recorder #3 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_INVALID_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1174) /* counter of TLB invalidate and configure invalidate */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CMD_SYNC_STS_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1178) /* cmd_sync counter and timeout indication */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_SYNC_MAX_TIME_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x117C) /* cmd_sync max time interval between request and response */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_CFG_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1180) /* To set parameters used by ATS module */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_TIMEOUT_L_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1184) /* ATC Invalidation timeout value config */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_TIMEOUT_H_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1188) /* ATC Invalidation timeout value config */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_PRIQ_IRPT_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x118C) /* ATS PRI queue interrupt aggregation configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1190) /* APAT ATS PASID config #0 for Xilinx Hook Test */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1194) /* APAT ATS PASID config #1 for Xilinx Hook Test */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1198) /* APAT ATS PASID config #2 for Xilinx Hook Test */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x119C) /* APAT ATS PASID config #3 for Xilinx Hook Test */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11A0) /* priv/exec bit config #0 for Xilinx Hook Test */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11A4) /* priv/exec bit config #1 for Xilinx Hook Test */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11A8) /* priv/exec bit config #2 for Xilinx Hook Test */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11AC) /* priv/exec bit config #3 for Xilinx Hook Test */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQID_PASID_PRI_EXC_CFG_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                              \
        0x11B0) /* PASID/PRI/EXC configure according to the request ID matched or not */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQID_PASID_PRI_EXC_RD_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE +                             \
        0x11B4) /* PASID/PRI/EXC read from the buffer according to the request ID matched or not */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_LKUP_REQ_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11C0) /* TLB lookup request counter */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_RETRIED_REQUEST_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11C4) /* TLB lookup retry request counter */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_RSP_SUCCESS_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11C8) /* TLB response success counter */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_RSP_FAULT_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11CC) /* TLB response fault counter */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_SCH_NOREISSUE_REQUEST_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11D0) /* No reissue request schedule counter */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_SCH_REISSUE_REQUEST_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11D4) /* Reissue request schedule counter */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_LKUP_AGING_REQ_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11D8) /* TLB lookup prediction aging request counter */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_AGING_REQ_RETRIED_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11DC) /* TLB lookup prediction aging request retry counter */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_ATS_TRS_STS_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11E0) /* ATS translate status dfx */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_ATS_INV_STS_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11E4) /* ATS invalidate status dfx */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_ATS_PRI_STS_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11E8) /* ATS PRI status dfx */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_ATS_TRS_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11EC) /* ATS translate request and completion counter dfx */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_ATS_INV_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11F0) /* ATS invalidate request and completion counter dfx */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_ATS_PRI_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11F4) /* ATS PRI request and  response counter dfx */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_SMMU_INV_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11F8) /* SMMU invalidate request and completion counter dfx */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_SMMU_PRI_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11FC) /* SMMU PRI request and  response counter dfx */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_GLB_CTRL_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1200) /* Global control the trigger behaviour */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1210) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1220) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1230) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1240) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1250) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1260) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1270) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1280) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1290) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12A0) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1214) /* The inbound traffic trigger sequence0 pattern high part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1224) /* The inbound traffic trigger sequence0 pattern high part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1234) /* The inbound traffic trigger sequence0 pattern high part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1244) /* The inbound traffic trigger sequence0 pattern high part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1254) /* The inbound traffic trigger sequence0 pattern high part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1264) /* The inbound traffic trigger sequence0 pattern high part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1274) /* The inbound traffic trigger sequence0 pattern high part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1284) /* The inbound traffic trigger sequence0 pattern high part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1294) /* The inbound traffic trigger sequence0 pattern high part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12A4) /* The inbound traffic trigger sequence0 pattern high part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1218) /* APAT trig TLP configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1228) /* APAT trig TLP configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1238) /* APAT trig TLP configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1248) /* APAT trig TLP configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1258) /* APAT trig TLP configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1268) /* APAT trig TLP configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1278) /* APAT trig TLP configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1288) /* APAT trig TLP configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1298) /* APAT trig TLP configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12A8) /* APAT trig TLP configure */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12B0) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12B4) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12B8) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12BC) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12C0) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12C4) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12C8) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12CC) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12D0) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12D4) /* The inbound traffic trigger sequence0 pattern low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12E0) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12F0) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1300) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1310) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1320) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1330) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1340) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1350) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1360) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1370) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12E4) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12F4) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1304) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1314) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1324) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1334) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1344) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1354) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1364) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1374) /* The inbound traffic trigger result low part */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12E8) /* APAT trig result prefix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12F8) /* APAT trig result prefix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1308) /* APAT trig result prefix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1318) /* APAT trig result prefix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1328) /* APAT trig result prefix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1338) /* APAT trig result prefix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1348) /* APAT trig result prefix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1358) /* APAT trig result prefix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1368) /* APAT trig result prefix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1378) /* APAT trig result prefix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1500) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1510) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1520) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1530) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1540) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1550) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1560) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1570) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1580) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1590) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15A0) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15B0) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C0) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15D0) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15E0) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15F0) /* MSI/MSIX control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1504) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1514) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1524) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1534) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1544) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1554) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1564) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1574) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1584) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1594) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15A4) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15B4) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C4) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15D4) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15E4) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15F4) /* MSI/MSIX address high 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1508) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1518) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1528) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1538) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1548) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1558) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1568) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1578) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1588) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1598) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15A8) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15B8) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C8) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15D8) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15E8) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15F8) /* MSI/MSIX address low 32bits */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_SMMU_BYPASS_PORT_EN_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1800) /* smmu bypass enable for each port configuration register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_ATOP_ENDIAN_FORMAT_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1804) /* Endian Format Control of inbound atomic operation */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_RX_FILTER_MODE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1808) /* IB Filter mode control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_SMMU_BYPASS_MEMATTR_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x180C) /* SNP/MEM_ATTR configuration for SMMU BYPASS */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_SDI_REG_REMAP_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1810) /* SDI NVME/DMA config register address remap */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_IB_POISON_PR_FORWARD_EN_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1814) /* Poison posted request forward control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_IB_BAR_DISP_SEL_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1818) /* Forward config based on BAR_NUM */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_PF_FUNC_SEL_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x181C) /* PF Function select */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_IB_ECO_REG_0_REG (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1820) /* ECO REG 0 \
                                                                                                          */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_IB_ECO_REG_1_REG (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1824) /* ECO REG 1 \
                                                                                                          */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_CTRL_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1830) /* Global control for SDI_THROUGH */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_ADDR_FILTER_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1834) /* Address filter control for SDI_THROUGH */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_PF_EN_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1840) /* PF Remap Enable for SDI_THROUGH */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_PF_REMAP_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1844) /* PF Remap control for SDI_THROUGH */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_PF_VF_START_FUN_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1848) /* Start function number configuration of PF for SDI_THROUGH */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_PF_VF_NUM_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x184C) /* Number of VF for each PF */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1880) /* Enable control for address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1890) /* Enable control for address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18A0) /* Enable control for address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18B0) /* Enable control for address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18C0) /* Enable control for address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18D0) /* Enable control for address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18E0) /* Enable control for address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18F0) /* Enable control for address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1884) /* Memory attribute control of address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1894) /* Memory attribute control of address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18A4) /* Memory attribute control of address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18B4) /* Memory attribute control of address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18C4) /* Memory attribute control of address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18D4) /* Memory attribute control of address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18E4) /* Memory attribute control of address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18F4) /* Memory attribute control of address window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1888) /* Address window control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1898) /* Address window control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18A8) /* Address window control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18B8) /* Address window control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18C8) /* Address window control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18D8) /* Address window control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18E8) /* Address window control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18F8) /* Address window control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x188C) /* Address mask control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x189C) /* Address mask control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18AC) /* Address mask control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18BC) /* Address mask control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18CC) /* Address mask control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18DC) /* Address mask control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18EC) /* Address mask control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18FC) /* Address mask control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_DELAY_CTRL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1940) /* IOB RX NPR delay control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_DELAY_CTRL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1944) /* IOB RX NPR delay control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_DELAY_CTRL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1948) /* IOB RX NPR delay control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_DELAY_CTRL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1950) /* IOB RX PR delay control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_DELAY_CTRL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1954) /* IOB RX PR delay control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_DELAY_CTRL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1958) /* IOB RX PR delay control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_DELAY_CTRL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1960) /* IOB RX CPL delay control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_DELAY_CTRL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1964) /* IOB RX CPL delay control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_DELAY_CTRL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1968) /* IOB RX CPL delay control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_0_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A00) /* Base address 0 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_0_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A80) /* Base address 0 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_0_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B00) /* Base address 0 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_0_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B80) /* Base address 0 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_0_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A04) /* Space Size for Base address 0 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_0_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A84) /* Space Size for Base address 0 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_0_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B04) /* Space Size for Base address 0 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_0_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B84) /* Space Size for Base address 0 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_1_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A08) /* Base address 1 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_1_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A88) /* Base address 1 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_1_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B08) /* Base address 1 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_1_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B88) /* Base address 1 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_1_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A0C) /* Space Size for Base address 1 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_1_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A8C) /* Space Size for Base address 1 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_1_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B0C) /* Space Size for Base address 1 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_1_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B8C) /* Space Size for Base address 1 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_2_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A10) /* Base address 2 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_2_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A90) /* Base address 2 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_2_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B10) /* Base address 2 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_2_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B90) /* Base address 2 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_2_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A14) /* Space Size for Base address 2 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_2_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A94) /* Space Size for Base address 2 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_2_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B14) /* Space Size for Base address 2 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_2_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B94) /* Space Size for Base address 2 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_3_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A18) /* Base address 3 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_3_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A98) /* Base address 3 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_3_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B18) /* Base address 3 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_3_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B98) /* Base address 3 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_3_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A1C) /* Space Size for Base address 3 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_3_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A9C) /* Space Size for Base address 3 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_3_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B1C) /* Space Size for Base address 3 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_3_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B9C) /* Space Size for Base address 3 of the P2P Memory space */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_0_REG                                                             \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A30) /* For the inbound completion and message, uses the host bridge bus \
                                                     range to determine the target Peer2Peer host bridge */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_1_REG                                                             \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AB0) /* For the inbound completion and message, uses the host bridge bus \
                                                     range to determine the target Peer2Peer host bridge */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_2_REG                                                             \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B30) /* For the inbound completion and message, uses the host bridge bus \
                                                     range to determine the target Peer2Peer host bridge */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_3_REG                                                             \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BB0) /* For the inbound completion and message, uses the host bridge bus \
                                                     range to determine the target Peer2Peer host bridge */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A34) /* P2P Destiantion id route address[47:16] configuration */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AB4) /* P2P Destiantion id route address[47:16] configuration */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B34) /* P2P Destiantion id route address[47:16] configuration */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BB4) /* P2P Destiantion id route address[47:16] configuration */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A38) /* P2P Route control register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AB8) /* P2P Route control register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B38) /* P2P Route control register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BB8) /* P2P Route control register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ATTR_CTRL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A3C) /* P2P Memory Attribute Control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ATTR_CTRL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1ABC) /* P2P Memory Attribute Control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ATTR_CTRL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B3C) /* P2P Memory Attribute Control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ATTR_CTRL_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BBC) /* P2P Memory Attribute Control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CTRL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A40) /* P2P credit Control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CTRL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AC0) /* P2P credit Control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CTRL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B40) /* P2P credit Control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CTRL_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BC0) /* P2P credit Control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_GLOBAL_CTRL_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E00) /* Global control of HAQ */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_01_ATTR_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E04) /* Attribute of HAQ Message Channel 0/1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_23_ATTR_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E08) /* Attribute of HAQ Message Channel 2/3 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_0_ADDR_L_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E10) /* Low address for message channel 0 to POE */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_0_ADDR_H_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E14) /* High address for message channel 0 to POE */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_1_ADDR_L_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E18) /* Low address for message channel 1 to POE */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_1_ADDR_H_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E1C) /* High address for message channel 1 to POE */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_2_ADDR_L_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E20) /* Low address for message channel 2 to POE */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_2_ADDR_H_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E24) /* High address for message channel 2 to POE */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_3_ADDR_L_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E28) /* Low address for message channel 3 to POE */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_3_ADDR_H_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E2C) /* High address for message channel 3 to POE */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_CFG_WIN_SEL_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E30) /* Config window select control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_WIN_CTRL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E40) /* Queue window Contorl register 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_WIN_CTRL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E44) /* Queue window Contorl register 1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_WIN_CTRL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E48) /* Queue window Contorl register 2 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_WIN_BASE_L_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E50) /* Base address of Queue window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_WIN_BASE_H_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E54) /* Base address of Queue window */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_RD_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F00) /* tph stash table read */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_WR_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F04) /* tph stash table write */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_STIDX_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F08) /* stash table r/w stdix */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_WDATA_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F0C) /* stash tabel write data */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_RDATA_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F10) /* stash table read data */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_BYPASS_PORT_EN_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F14) /* TPH bypass enable for each port configuration register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F20) /* tph replace control for each request port */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F24) /* tph replace control for each request port */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F28) /* tph replace control for each request port */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F2C) /* tph replace control for each request port */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F30) /* tph replace control for each request port */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F34) /* tph replace control for each request port */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F38) /* tph replace control for each request port */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F3C) /* tph replace control for each request port */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F40) /* tph replace control for each request port */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F44) /* tph replace control for each request port */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_WEIGHT_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2300) /* AXIM_ARB arbitration weight. */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_RATE_CTRL_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2304) /* AXIM_ARB request rate control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_RD_OST_NUM_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2308) /* AXIM_ARB read outstanding number threshold */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_TARGET_LAT_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x230C) /* AXIM_ARB target latency */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_LAT_SEL_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2310) /* AXIM_ARB latency dfx control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_RDY_CTRL_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2314) /* AXIM_ARB latency dfx control */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_STATE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2340) /* State of AXIM_ARB */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_CNT_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2360) /* counter of AXIM_M0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_CNT_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2364) /* counter of AXIM_M0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_CNT_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2368) /* counter of AXIM_M1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_CNT_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x236C) /* counter of AXIM_M1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_AR_LAT_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2380) /* AXI AR latency 0 of Master 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_AR_LAT_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2384) /* AXI AR latency 1 of Master 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_AW_LAT_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2388) /* AXI AW latency 0 of Master 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_AW_LAT_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x238C) /* AXI AW latency 1 of Master 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_AR_LAT_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2390) /* AXI AR latency 0 of Master 1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_AR_LAT_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2394) /* AXI AR latency 1 of Master 1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_AW_LAT_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2398) /* AXI AW latency 0 of Master 1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_AW_LAT_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x239C) /* AXI AW latency 1 of Master 1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_CURR_SEQ_NUM_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23A0) /* Current sequence number of HAQ message channel */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_TRANS_CNT_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23A4) /* Counter 0 of HAQ packet */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_SEQ_NUM_STS_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23A8) /* Sequence number state of haq channel 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_SEQ_NUM_STS_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23AC) /* Sequence number state of haq channel 1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_TRANS_CNT_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23B0) /* Counter 1 of HAQ packet */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_SEQ_NUM_STS_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23B4) /* Sequence number state of haq channel 2 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_SEQ_NUM_STS_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23B8) /* Sequence number state of haq channel 3 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_SEQ_STS0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23C0) /* P2P Sequence number Status for hostbridge 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_SEQ_STS1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23C4) /* P2P Sequence number Status for hostbridge 1 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_SEQ_STS2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23C8) /* P2P Sequence number Status for hostbridge 2 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_SEQ_STS3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23CC) /* P2P Sequence number Status for hostbridge 3 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_STS_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23D0) /* P2P dfx status for hostbridge 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_STS_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23D4) /* P2P dfx status for hostbridge 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_STS_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23D8) /* P2P dfx status for hostbridge 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_STS_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23DC) /* P2P dfx status for hostbridge 0 */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_0_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x0) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_1_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x4) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_2_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x8) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_3_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_4_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_5_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x14) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_6_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_7_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_8_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_9_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x24) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_10_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x28) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_11_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2C) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_12_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x30) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_13_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x34) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_14_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x38) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_15_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3C) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_16_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x40) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_17_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x44) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_18_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x48) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_19_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x4C) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_20_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x50) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_21_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x54) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_22_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x58) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_23_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x5C) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_24_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x60) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_25_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x64) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_26_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x68) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_27_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x6C) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_28_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x70) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_29_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x74) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_30_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x78) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_31_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x7C) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_32_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x80) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_33_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x84) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_34_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x88) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_35_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x8C) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_36_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x90) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_37_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x94) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_38_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x98) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_39_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x9C) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_40_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA0) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_41_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA4) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_42_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA8) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_43_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_44_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB0) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_45_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB4) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_46_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB8) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_47_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBC) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_48_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC0) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_49_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC4) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_50_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC8) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_51_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xCC) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_52_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD0) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_53_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD4) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_54_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD8) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_55_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xDC) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_56_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE0) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_57_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE4) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_58_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE8) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_59_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xEC) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_60_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF0) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_61_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF4) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_62_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF8) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_63_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xFC) /* configure the stash table */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_TPH_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x200) /* configure the tph mode register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_TPH_BANDWIDTH_EXCEED_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x203) /* configure tph bandwidth filter register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_PH_MAP_TO_TARGET_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x204) /* configure ph mapping register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_DATA_TYPE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x205) /* configure ph mapping register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_DATA_TYPE_DESCRIPTOR_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x206) /* configure ph mapping register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_DATA_TYPE_PACKET_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x207) /* configure ph mapping register */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_WR_ADJUST_BW_LIMIT_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x208) /* write after latency adjust bandwidth limit result */
#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_STAT_TLP_BW_AVERAGE_REG \
    (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x209) /* average tlp bandwidth result */

/* HIPCIEC_AP_MG_REG Base address of Module's Register */
#define CSR_HIPCIEC_AP_MG_REG_BASE (0x8000)

/* **************************************************************************** */
/*                      HIPCIEC_AP_MG_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC_AP_MG_REG_PCIE_ERR_MAPPING_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE +                  \
        0x0) /* CE(ERR_COR)/UNF(ERR_NONFATAL)/UF(ERR_FATAL)/NI(NORMAL_INT) mapping to ERI/FHI/SPI0/SPI1 */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_ENA_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x8) /* CE(ERR_COR) interrupt enable of each source. */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_UNF_ENA_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10) /* UNF(ERR_NONFATAL) interrupt enable of each source. */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_UF_ENA_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x18) /* UF(ERR_FATAL) interrupt enable of each source. */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_STATUS_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x20) /* CE(ERR_COR) interrupt status of each source. */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_UNF_STATUS_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x28) /* UNF(ERR_NONFATAL)  interrupt status of each source. */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_UF_STATUS_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x30) /* UF(ERR_FATAL)  interrupt status of each source. */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_NI_ENA_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x38) /* NI(NORMAL_INT) interrupt enable of each source */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_NI_STATUS_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x3C) /* NI(NORAML_INT)  interrupt status of each source */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x40) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x48) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x50) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_3_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x58) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_4_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x60) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_5_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x68) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_6_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x70) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_7_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x78) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_8_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x80) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_9_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x88) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_10_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x90) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_11_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x98) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_12_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xA0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_13_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xA8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_14_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xB0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_15_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xB8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_16_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xC0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_17_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xC8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_18_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xD0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_19_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xD8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_20_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xE0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_21_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xE8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_22_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xF0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_23_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0xF8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_24_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x100) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_25_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x108) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_26_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x110) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */
#define CSR_HIPCIEC_AP_MG_REG_CFG_INTX_CLR_EN_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x400) /* Config the INTx clear of each Port. */
#define CSR_HIPCIEC_AP_MG_REG_CFG_INTX_DEASSERT_MODE_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x404) /* Config the INTx deassert mode of each Port. */
#define CSR_HIPCIEC_AP_MG_REG_CFG_ODR_DISP_CTRL_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x408) /* IOB RX dispatch dfx select control register */
#define CSR_HIPCIEC_AP_MG_REG_CFG_PORT_ERR_CLR_EN_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x40C) /* the clear enable of the ni/ce/ufe/fe counter of each source. */
#define CSR_HIPCIEC_AP_MG_REG_CFG_ODR_DISP_MISC_CTRL_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x410) /* IOB_RX_DISP bdoor register. */
#define CSR_HIPCIEC_AP_MG_REG_DFX_PORT_INTX_PENDING_CNT_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x500) /* INTx Pending Conute DFX register */
#define CSR_HIPCIEC_AP_MG_REG_DFX_CORE_INTX_CNT_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x504) /* INTx Conute DFX register \
                                                                                          */
#define CSR_HIPCIEC_AP_MG_REG_DFX_PORT_ERR_CNT0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x510) /* NI and CE conuter DFX register */
#define CSR_HIPCIEC_AP_MG_REG_DFX_PORT_ERR_CNT1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x514) /* NFE and FE counter DFX register */
#define CSR_HIPCIEC_AP_MG_REG_DFX_ODR_P_CNT_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x520) /* Odr channel post tlp counter register */
#define CSR_HIPCIEC_AP_MG_REG_DFX_ODR_NP_CNT_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x524) /* Odr channel non post tlp counter register */
#define CSR_HIPCIEC_AP_MG_REG_AP_RAM_TIMING_CFG_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x800) /* sram timing config for all of the SRAM in AP module */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TOP_CTRL_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1000) /* MCTP Top Control Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_CTRL_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1004)   /* MCTP Control Register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_CTRL_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1204)   /* MCTP Control Register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_CTRL_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1404)   /* MCTP Control Register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV0_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1008)   /* MCTP Reserved Register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV0_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1208)   /* MCTP Reserved Register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV0_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1408)   /* MCTP Reserved Register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV1_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x100C)   /* MCTP Reserved Register 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV1_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x120C)   /* MCTP Reserved Register 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV1_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x140C)   /* MCTP Reserved Register 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV2_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1010)   /* MCTP Reserved Register 2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV2_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1210)   /* MCTP Reserved Register 2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV2_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1410)   /* MCTP Reserved Register 2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INT_MAPPING_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1014) /* Interrupt mapping 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INT_MAPPING_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1214) /* Interrupt mapping 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INT_MAPPING_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1414) /* Interrupt mapping 2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_STAT_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1018) /* Interrupt Status Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_STAT_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1218) /* Interrupt Status Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_STAT_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1418) /* Interrupt Status Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SET_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x101C) /* Interrupt Set-Enable Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SET_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x121C) /* Interrupt Set-Enable Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SET_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x141C) /* Interrupt Set-Enable Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_MASK_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1020) /* Interrupt Mask Register \
                                                                                            */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_MASK_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1220) /* Interrupt Mask Register \
                                                                                            */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_MASK_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1420) /* Interrupt Mask Register \
                                                                                            */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SOURCE_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1024) /* Interrupt Source Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SOURCE_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1224) /* Interrupt Source Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SOURCE_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1424) /* Interrupt Source Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_0_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1028) /* RX interrupt control register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_0_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1228) /* RX interrupt control register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_0_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1428) /* RX interrupt control register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1030) /* RX Queue Pempty Threshold Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1230) /* RX Queue Pempty Threshold Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1430) /* RX Queue Pempty Threshold Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_1_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1034) /* RX interrupt control register 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_1_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1234) /* RX interrupt control register 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_1_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1434) /* RX interrupt control register 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_2_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1038) /* RX interrupt control register 2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_2_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1238) /* RX interrupt control register 2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_2_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1438) /* RX interrupt control register 2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_3_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x103C) /* RX interrupt control register 3 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_3_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x123C) /* RX interrupt control register 3 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_3_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x143C) /* RX interrupt control register 3 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1040) /* RX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1240) /* RX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1440) /* RX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1044) /* RX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1244) /* RX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1444) /* RX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1048) /* RX Queue Depth. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1248) /* RX Queue Depth. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1448) /* RX Queue Depth. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1050) /* RX Queue Head Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1250) /* RX Queue Head Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1450) /* RX Queue Head Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1054) /* RX Queue Tail Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1254) /* RX Queue Tail Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1454) /* RX Queue Tail Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1060) /* TX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1260) /* TX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1460) /* TX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1064) /* TX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1264) /* TX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1464) /* TX Queue base address register. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1068) /* TX Queue Depth. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1268) /* TX Queue Depth. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1468) /* TX Queue Depth. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1070) /* TX Queue Head Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1270) /* TX Queue Head Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1470) /* TX Queue Head Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1074) /* TX Queue Tail Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1274) /* TX Queue Tail Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1474) /* TX Queue Tail Pointer. */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1080) /* RX AXI Write Error Address */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1280) /* RX AXI Write Error Address */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1480) /* RX AXI Write Error Address */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1084) /* RX AXI Write Error Address */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1284) /* RX AXI Write Error Address */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1484) /* RX AXI Write Error Address */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK0_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10A0) /* TLP Header Check Register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK0_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12A0) /* TLP Header Check Register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK0_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14A0) /* TLP Header Check Register 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK1_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10A4) /* TLP Header Check Register 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK1_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12A4) /* TLP Header Check Register 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK1_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14A4) /* TLP Header Check Register 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK2_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10A8) /* TLP Header Check Register 2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK2_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12A8) /* TLP Header Check Register 2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK2_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14A8) /* TLP Header Check Register 2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_0_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10B0) /* Counter for error tx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_0_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12B0) /* Counter for error tx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_0_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14B0) /* Counter for error tx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_1_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10B4) /* Counter for error tx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_1_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12B4) /* Counter for error tx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_1_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14B4) /* Counter for error tx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_0_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10B8) /* Counter for error rx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_0_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12B8) /* Counter for error rx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_0_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14B8) /* Counter for error rx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_1_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10BC) /* Counter for error rx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_1_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12BC) /* Counter for error rx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_1_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14BC) /* Counter for error rx message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_DATA_FIFO_STATUS_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10C0) /* FIFO status Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_DATA_FIFO_STATUS_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12C0) /* FIFO status Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_DATA_FIFO_STATUS_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14C0) /* FIFO status Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10C4) /* Threshold to drop RX message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12C4) /* Threshold to drop RX message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14C4) /* Threshold to drop RX message */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_CNT_0_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10C8) /* RX dropped message counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_CNT_0_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12C8) /* RX dropped message counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_CNT_0_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14C8) /* RX dropped message counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_0_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10CC) /* MCTP TX Routing Error Counter 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_0_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12CC) /* MCTP TX Routing Error Counter 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_0_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14CC) /* MCTP TX Routing Error Counter 0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_1_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10D0) /* MCTP TX Routing Error Counter 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_1_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12D0) /* MCTP TX Routing Error Counter 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_1_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14D0) /* MCTP TX Routing Error Counter 1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_0_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10D4) /* MCTP TX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_0_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12D4) /* MCTP TX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_0_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14D4) /* MCTP TX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_1_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10D8) /* MCTP TX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_1_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12D8) /* MCTP TX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_1_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14D8) /* MCTP TX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_2_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10DC) /* MCTP TX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_2_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12DC) /* MCTP TX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_2_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14DC) /* MCTP TX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_0_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10E0) /* MCTP RX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_0_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12E0) /* MCTP RX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_0_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14E0) /* MCTP RX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_1_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10E4) /* MCTP RX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_1_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12E4) /* MCTP RX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_1_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14E4) /* MCTP RX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_2_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10E8) /* MCTP RX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_2_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12E8) /* MCTP RX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_2_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14E8)                                                /* MCTP RX Packet Statistic */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_DEBUG_FSM_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10EC) /* FSM Status Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_DEBUG_FSM_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12EC) /* FSM Status Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_DEBUG_FSM_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14EC) /* FSM Status Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_MATCH_STAT_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10F0) /* MCTP Header Match Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_MATCH_STAT_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12F0) /* MCTP Header Match Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_MATCH_STAT_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14F0)                                          /* MCTP Header Match Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_DFX_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10F4) /* MCTP DFX Control Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_DFX_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12F4) /* MCTP DFX Control Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_DFX_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14F4) /* MCTP DFX Control Register */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_ECC_ERR_INJECTION_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10F8) /* MCTP ECC Error Injection */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_ECC_ERR_INJECTION_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12F8) /* MCTP ECC Error Injection */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_ECC_ERR_INJECTION_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14F8) /* MCTP ECC Error Injection */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10FC) /* MCTP RX 1-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12FC) /* MCTP RX 1-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14FC) /* MCTP RX 1-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1110) /* MCTP RX 2-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1310) /* MCTP RX 2-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1510) /* MCTP RX 2-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1114) /* MCTP TX 1-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1314) /* MCTP TX 1-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1514) /* MCTP TX 1-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1118) /* MCTP TX 2-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1318) /* MCTP TX 2-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1518) /* MCTP TX 2-bit ECC Error Counter */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x111C) /* MCTP Dropped Header DW0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x131C) /* MCTP Dropped Header DW0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x151C) /* MCTP Dropped Header DW0 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1120) /* MCTP Dropped Header DW1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1320) /* MCTP Dropped Header DW1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1520) /* MCTP Dropped Header DW1 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1124) /* MCTP Dropped Header DW2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1324) /* MCTP Dropped Header DW2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1524) /* MCTP Dropped Header DW2 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1128) /* MCTP Dropped Header DW3 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1328) /* MCTP Dropped Header DW3 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1528)                                             /* MCTP Dropped Header DW3 */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_AXUSER_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x112C) /* MCTP AXUSER */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_AXUSER_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x132C) /* MCTP AXUSER */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_AXUSER_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x152C) /* MCTP AXUSER */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1130) /* MCTP RX memory write request Stream ID */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1330) /* MCTP RX memory write request Stream ID */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1530) /* MCTP RX memory write request Stream ID */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_0_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1134) /* MCTP TX memory read request Stream ID */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_1_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1334) /* MCTP TX memory read request Stream ID */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_2_REG \
    (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1534) /* MCTP TX memory read request Stream ID */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_DFX_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x2018) /* MCTP_RC BC */
#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DISPATCH_DFX_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x201C)  /* MCTP RX Dispatch */

/* HIPCIEC_AP_INT_REG Base address of Module's Register */
#define CSR_HIPCIEC_AP_INT_REG_BASE (0x10000)

/* **************************************************************************** */
/*                      HIPCIEC_AP_INT_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC_AP_INT_REG_MSIX_VECTOR_NUM_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x0) /* MSIX Vector Number */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_COAL_CTRL_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0x4) /* MSIX Vector Coal Control Register */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_COAL_EVENT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x8) /* MSIX Coal Event Register */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_COAL_TIME_UNIT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xC) /* MSIX Coal Time Unit */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_MSG_ADDR_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x10)      /* MSIX Message Address */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_MSG_UP_ADDR_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x14)   /* MSIX Message up Address */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_MSG_DATA_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x18)      /* MSIX Message Data */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_VECTOR_CTRL_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x1C)   /* MSIX Vector Control */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_PENDING_BIT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x20)   /* MSIX Pending Bits */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_SRAM_INIT_STATUS_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0x24)                                                 /* MSIX sram initial status */
#define CSR_HIPCIEC_AP_INT_REG_SDI_ECO_REGISTER_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x28) /* ECO register */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_MISC_CTRL_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0x2C) /* Set Relaxed Ordering fields in MSI/MSIX message */
#define CSR_HIPCIEC_AP_INT_REG_RAS_INT_LEVEL_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x30)      /* RAS interrupt level */
#define CSR_HIPCIEC_AP_INT_REG_HOST_ACCESS_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x50) /* Host access tlp status \
                                                                                            */
#define CSR_HIPCIEC_AP_INT_REG_TLP_CNT_CFG_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x54)        /* Tlp count configure */
#define CSR_HIPCIEC_AP_INT_REG_HOST_TLP_CNT_0_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x58)     /* Host TLP Count0 */
#define CSR_HIPCIEC_AP_INT_REG_HOST_TLP_CNT_1_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x5C)     /* Host TLP Count1 */
#define CSR_HIPCIEC_AP_INT_REG_DMA_INPUT_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x60)   /* dma input status */
#define CSR_HIPCIEC_AP_INT_REG_DMA_OUTPUT_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x64)  /* dma output status */
#define CSR_HIPCIEC_AP_INT_REG_NVME_INPUT_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x68)  /* nvme input status */
#define CSR_HIPCIEC_AP_INT_REG_NVME_OUTPUT_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x6C) /* nvme output status */
#define CSR_HIPCIEC_AP_INT_REG_FSM_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x70)         /* fsm status */
#define CSR_HIPCIEC_AP_INT_REG_LINK_DOWN_IDLE_STATUS_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0x74)                                                    /* Link down idle status */
#define CSR_HIPCIEC_AP_INT_REG_ECC_ERR_INT_SRC_STS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x78) /* ECC error int src */
#define CSR_HIPCIEC_AP_INT_REG_ECC_ERR_MASK_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x7C)        /* ECC Error Mask */
#define CSR_HIPCIEC_AP_INT_REG_ECC_ERR_INT_STS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x80)     /* ECC error int sts */
#define CSR_HIPCIEC_AP_INT_REG_ECC_ERR_INJECT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x84)      /* ECC Error inject */
#define CSR_HIPCIEC_AP_INT_REG_ECC_ERR_CNT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x88)         /* ECC Error counter */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_TBL_ECC_ERR_ADDR_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0x8C) /* msix tbl ECC error address */
#define CSR_HIPCIEC_AP_INT_REG_COAL_TBL_ECC_ERR_ADDR_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0x90)                                             /* coal tbl ECC error address */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_RO_CE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x94)   /* msix ce ro register */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_RO_NFE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x98)  /* msix nfe ro register */
#define CSR_HIPCIEC_AP_INT_REG_MSIX_RO_FE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x9C)   /* msix fe ro register */
#define CSR_HIPCIEC_AP_INT_REG_SET_MSIX_INT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xA0) /* set msix interrupt */
#define CSR_HIPCIEC_AP_INT_REG_ABNORMAL_INT_STS_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0xA4) /* interrupt status of INT abnormal */
#define CSR_HIPCIEC_AP_INT_REG_ABNORMAL_INT_MASK_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0xA8) /* interrupt mask of INT abnormal */
#define CSR_HIPCIEC_AP_INT_REG_ABNORMAL_INT_SET_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xAC) /* setting interrupt */
#define CSR_HIPCIEC_AP_INT_REG_ABNORMAL_INT_RO_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0xB0) /* interrupt indicater of INT abnormal */
#define CSR_HIPCIEC_AP_INT_REG_DMA_ERR_FUNC_VEC_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0xB4) /* DMA function or vector access error register */
#define CSR_HIPCIEC_AP_INT_REG_NVME_ERR_FUNC_VEC_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0xB8) /* NVME function or vector access error register */
#define CSR_HIPCIEC_AP_INT_REG_INT_IDBO_CTRL_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0xBC) /* Set ID-Based Ordering  fields in MSI/MSIX message */
#define CSR_HIPCIEC_AP_INT_REG_INT_NS_CTRL_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0xC0) /* Set No Snoop fields in MSI/MSIX message */
#define CSR_HIPCIEC_AP_INT_REG_TL_REG_DFX_ADDR_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xC4) /* TL_REG DFX address */
#define CSR_HIPCIEC_AP_INT_REG_TL_REG_DFX_DATA_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xC8) /* TL_REG DFX data */
#define CSR_HIPCIEC_AP_INT_REG_ERR_FUNC_VEC_CNT_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0xCC) /* Record how much times of function error and vector error occurs. */
#define CSR_HIPCIEC_AP_INT_REG_INT_CTRL_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xD0) /* Ctrling signal of INTX/MSI/MSIX. \
                                                                                  */
#define CSR_HIPCIEC_AP_INT_REG_INT_TPH_CTRL0_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0xE0) /* Set TH/ST/PH fields in MSI/MSIX message of PF0 and PF1 */
#define CSR_HIPCIEC_AP_INT_REG_INT_TPH_CTRL1_REG \
    (CSR_HIPCIEC_AP_INT_REG_BASE + 0xE4) /* Set TH/ST/PH fields in MSI/MSIX message of PF2 and PF3 */
#define CSR_HIPCIEC_AP_INT_REG_NET_ECAM_BUS_NUM_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x100) /* Network ECAM Bus number \
                                                                                           */
#define CSR_HIPCIEC_AP_INT_REG_NET_PF_NUM_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x104)       /* Network PF Number */
#define CSR_HIPCIEC_AP_INT_REG_NET_FIRST_VF_NUM_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x108) /* Network VF First  Number \
                                                                                           */
#define CSR_HIPCIEC_AP_INT_REG_NET_VF_STRIDE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x10C)    /* Network VF Stride */
#define CSR_HIPCIEC_AP_INT_REG_NET_ECAM_BASE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x110)    /* Network ECAM BASE */
#define CSR_HIPCIEC_AP_INT_REG_ERR_RESPONSE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x114)     /* Sync error response */

#endif // PCIE4_REG_OFFSET_H
